Systems are known in which a high-speed serial data stream is transmitted without an accompanying clock signal. In a process known as clock-data recovery (CDR), the receiver recovers the data bits from the incoming data stream using signal transitions in the incoming data stream to regenerate or recover a clock signal. As illustrated in FIG. 1, a CDR system 10 in such a receiver may include phase-locked loop (PLL) circuitry 12 that comprises a phase detector 14, a loop filter 15, and a voltage-controlled oscillator (VCO) 16. The PLL circuitry 12 uses the incoming data stream (DATA) to generate an output clock signal (OUT), which is provided as feedback to phase detector 14. The output clock signal can be used to sample the data and thereby synchronize or re-time the data stream to the generated clock signal. Thus, both a clock signal and data synchronized with the clock signal are recovered from the incoming data stream.
Although FIG. 1 shows a single-loop CDR system 10, split-loop systems are also known. In a split-loop CDR system (not shown), a first path includes circuitry that phase-aligns the generated clock signal with the incoming data, while a second path includes circuitry that determines the frequency of the incoming data signal.
As further illustrated in FIG. 1, CDR system 10 includes a clock phase generator 18 that uses the output clock to generate several (e.g., four) additional clock signals, separated equally in phase from each other. A sampling circuit 20 uses the additional clock signals to sample the data bits. Using more than one clock signal to sample the data bits can provide more accurate results in sampling the signal levels and edges than if only a single clock signal were used.
The above-described PLL circuitry 12 generally maintains the recovered or re-generated (output) clock signal in alignment with, i.e., phase-locked to, the incoming data stream by making small adjustments to the phase of the output clock signal in response to small phase changes in the incoming data signal transitions. However, if PLL circuitry 12 experiences a large phase change in the incoming data stream, such as between 90 and 180 degrees, it may take an unacceptably long amount of time to re-lock the clock signal to the incoming data stream.